1. Field of the Invention
This invention relates to integrated circuits (ICs), and more particularly, to the placement of circuitry and interconnections on integrated circuits.
2. Description of the Related Art
As the feature sizes of devices implemented on ICs have shrunk, the number of devices has increased. Operating speeds of ICs has similarly increased. The increase in the number of devices on a single IC has resulted in a corresponding increase in the number of interconnections. Furthermore, since operating speeds of ICs have increased, the apparent distance between some circuits has increased, in some cases such that signal travel times cross clock boundaries. For many long distance signal routes, repeater circuits are required, regardless of whether a clock boundary is crossed.
The large number of interconnections necessitated by the large number of devices on an IC can consume a significant amount of area. Furthermore, the number of interconnections can cause the paths of some to interfere with others. In order to overcome this, many of the interconnections include bends and transitions to other layers through vias in order to avoid other interconnections. While this may enable a large number of interconnections to be implemented on a single IC, it can cause some performance issues. For example, parasitic resistances may be larger for signal interconnections that include a number of bends and vias that are implemented to avoid collisions with other interconnections. The increased resistance may in turn result in longer signal propagation times, which can limit the operating frequency of the IC and/or necessitate additional state element circuits when the propagation time for particular interconnects crosses a clock boundary.